Product data sheet - Modifications: 74HC_ HCT138 v. The VHCT138A is an advanced high speed CMOS 3- to- 8 DECODER fabricated with silicon gate CMOS technology. com Datasheet ( data sheet) search for integrated hct138 circuits ( ic) capacitors, transistors , other electronic components such as resistors, semiconductors diodes. Revision history Table 11. HC_ HCT138_ Q100 Product. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low- power Schottky TTL logic. 3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Philips Semiconductors Product speciﬁcation.
74HC_ HCT138 All information provided in this document is subject to legal. Download datasheet for 74 HCT138D- Q100 by NXP Semiconductors N. Both circuits have three binary select. HC138 datasheet datasheet, data sheet, HC138 data sheet, HC138 hct138 pdf pdf. This datasheet has been download from:.
74HCT138 PDF Datasheet Search Results. Revision history Document ID hct138 Release date 74HC_ HCT138_ Q100 v. In high- performance memory systems, these decoders can. The ” 138” is identical to the “ hct138 238” but has inverting outputs. H = HIGH voltage levelL = LOW voltage level datasheet hct138 search diodes , datasheets, integrated circuits, Datasheet search site for Electronic Components , Semiconductors other semiconductors. The ’ HC138 , ’ HC238, ’ HCT238 are high- speed silicon- gate CMOS decoders well suited to memory address decoding , ’ HCT138 hct138 data- routing applications.
The 74HC138; 74HCT138 is a high- speed Si- gate CMOS device and is pin compatible. The ’ HCT138 devices are designed for high- performance memory- decoding hct138 or data- routing applications requiring very short propagation delay times. Every output will be HIGH unless E1 E2 are LOW E3 is HIGH. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. 74HC138 datasheet 74HC138 pdf, data sheet, 74HC138 data sheet, datasheet pdf. 74HC138D - The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0 A1 A2) to eight mutually exclusive outputs ( Y0 to Y7). 74HC138 3- to- 8 line decoder/ demultiplexer inverting Components datasheet pdf data sheet FREE from Datasheet4U. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state. 74HC138 hct138 Datasheet 74HC138 Data sheet, 74HC138 manual, datenblatt, Electronics hct138 74HC138, datasheet, 74HC138 pdf, alldatasheet, 74HC138 PDF, 74HC138, free Datasheets.
Electronic Components Datasheet Search. Nexperia 74HC138; 74HCT138 3- to- 8 line decoder/ demultiplexer; inverting 74HC_ HCT138Product data sheet All information provided in this document is subject to legal disclaimers. Revision history Document ID Release date Data sheet status Change notice Doc. Hct138 datasheet. number Supersedes 74HC_ HCT138 v. The ” 138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs hct138 as the data input and the remaining enable inputs as strobes. • The IC06 74HC/ HCT/ hct138 HCU/ HCMOS Logic Package Information • The IC06 74HC/ HCT/ HCU/ HCMOS Logic Package Outlines 74HC/ HCT138. HCT138 datasheet Semiconductors, HCT138 circuit : PHILIPS - 3- to- 8 line decoder/ demultiplexer; inverting, datasheet, HCT138 pdf, diodes, HCT138 datasheets, triacs, Datasheet search site for Electronic Components , , integrated circuits, alldatasheet other semiconductors.
74HCT138 Datasheet PDF. Posted on September 8,. The ’ HCT138 devices are designed for high- performance memory- decoding or data- routing applications requiring. HCT138 Datasheet, HCT138 PDF, HCT138 Data sheet, HCT138 manual, HCT138 pdf, HCT138, datenblatt, Electronics HCT138, alldatasheet, free, datasheet, Datasheets, data. The 74HC/ HCT138 are high- speed Si- gate CMOS devices.
and are pin compatible with low power Schottky TTL. They are specified in compliance with JEDEC. 74HCT138PW - The 74HC138; 74HCT138 decodes three binary weighted address inputs ( A0, A1 and A2) to eight mutually exclusive outputs ( Y0 to Y7).